(1) Field of the Invention
The present method relates to methods used to fabricate semiconductor devices, and more specifically to a method used to increase the etch rate selectivity of a dry etch procedure employed for the definition of a conductive gate structure.
(2) Description of Prior Art
Micro-miniaturization, or the ability to fabricate semiconductor devices with sub-micron features, has allowed performance increases for the sub-micron MOSFET devices to be realized, basically via reductions in performance degrading junction capacitances. Sub-micron MOSFET devices are also being fabricating featuring thin silicon dioxide gate insulator layers, used to allow operating voltages to be decreased. The use of thinner silicon dioxide layers however can present higher leakage currents than counterparts comprised with thicker silicon dioxide gate insulator layers. Formation of nitrided gate insulator layers such as a nitrided silicon dioxide layer, can however reduce leakage in thin gate insulator layers. The higher dielectric constant of the nitrided gate insulator layer when compared to non-nitrided silicon dioxide gate insulator counterparts, as well as maintaining an equivalent oxide thickness (EOT), result in lower leakage currents thus making nitrided silicon dioxide gate insulator layer an attractive option for sub-micron MOSFET devices.
The employment of nitrided gate insulator layer can however present difficulties during definition of an overlying conductive gate structure. Selective dry etch procedures employed for gate structure definition are designed to terminate at the exposure of the gate insulator layer in areas not covered by the now defined gate structure, at dry etch end point. This is accomplished via a high etch rate ratio between the conductive gate structure material, such as polysilicon, and the underlying gate insulator material, such as silicon dioxide. However the presence of the underlying nitrided silicon dioxide layer, featuring an undesirable faster etch rate than non-nitrided silicon dioxide, results in a decreased etch rate ratio. The lower etch rate selectivity resulting form the presence of nitrided silicon dioxide underlays adds complexity and difficulty to end point control for the conductive gate structure, selective dry etch definition procedure, sometimes resulting in break through of the nitrided silicon dioxide layer and unwanted pitting or damage of underlying semiconductor substrate regions. The damaged semiconductor regions, subsequently used to accommodate MOSFET features such as source/drain regions, can result in decreased MOSFET yield, performance and reliability.
The present invention will describe a procedure in which nitrided gate insulator layers can be employed as a component of a sub-micron MOSFET device, while still allowing the high etch rate ratio of conductive gate material to nitrided gate insulator material to be maintained. This is accomplished via a simple process step performed to the nitrided gate insulator material prior to deposition of the material used for the conductive gate structure. Prior art such as Miyazaki, in U.S. Pat. No. 6,335,278 B1, as well as Houston et al, in U.S. Pat. No. 6,569,741 B2, have described annealing procedures employed to remedy device leakage problems. However none of the above prior art offer the process described in this present invention in which a nitrided gate insulator layer is treated prior to deposition of a conductive gate material to maintain a high etch rate ratio for a subsequent dry etch procedure employed for the definition of a conductive gate structure.